Query on VHDL generics in packages -

i have written simple vhdl code add 2 matrices containing 32 bit floating point numbers. matrix dimensions have been defined in package. currently, specify matrix dimensions in vhdl code , use corresponding type package. however, use generic in design deal matrices of different dimensions. have somehow use right type defined in package. how go doing this? current vhdl code below.

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use work.mat_pak.all;  entity newproj     port ( clk : in  std_logic;            clr : in  std_logic;            start : in  std_logic;            a_in : in  t2;            b_in : in  t2;            aplusb : out  t2;            parallel_add_done : out  std_logic); end newproj;  architecture behavioral of newproj component add   port (     : in std_logic_vector(31 downto 0);     b : in std_logic_vector(31 downto 0);     clk : in std_logic;     sclr : in std_logic;     ce : in std_logic;     result : out std_logic_vector(31 downto 0);     rdy: out std_logic   ); end component;   signal temp_out: t2 := (others=>(others=>(others=>'0'))); signal add_over: t2bit:=(others=>(others=>'0')); signal check_all_done,init_val: std_logic:='0'; begin     init_val <= '1';     g0: k in 0 1 generate                 g1: m in 0 1 generate                             add_instx: add port map(a_in(k)(m), b_in(k)(m),     clk, clr, start, temp_out(k)(m), add_over(k)(m));                 end generate;            end generate;          g2: k in 0 1 generate                 g3: m in 0 1 generate                         check_all_done <= add_over(k)(m) , init_val;                 end generate;            end generate;          p1_add:process(check_all_done,temp_out)         begin             aplusb <= temp_out;             parallel_add_done <= check_all_done;                     end process;  end behavioral; 

my package below

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all;      package mat_pak       subtype small_int integer range 0 2;      type t22 array (0 1) of std_logic_vector(31 downto 0);     type t2 array (0 1) of t22; --2*2 matrix      type t22bit array (0 1) of std_logic;     type t2bit array (0 1) of t22bit; --2*2 matrix bit      type t33 array (0 2) of std_logic_vector(31 downto 0);     type t3 array (0 2) of t33; --3*3 matrix  end mat_pak; 

any suggestions welcome. thank you.

there logical issues design.

first, there's maximum number of ports sub-hierarchy design can tolerate, have 192 'bits' of matrix inputs , outputs. believe number should configurable?

at point fit in large fpga devices, , shortly thereafter not fit there either.

imagining operation taking variable number of clocks in add , parallel_add_done signifies when aplusb datum available comprised of elements of matrix array contributed instantiated add components, individual rdy signals anded together. if adds take same amount of time take rdy of them (if silicon not deterministic not usable, there registers in add).

the nested generate statements assign result of , between add_over(k,m) , init_val (which synthesis constant of 1). effect or wire anding add_over(k.m) bits (which doesn't work in vhdl , not achievable in synthesis, either).

note showed proper indexing method 2 dimensional arrays.

using jonathan's method of sizing matrixes:

library ieee; use ieee.std_logic_1164.all;  package mat_pak      type matrix  array (natural range <>, natural range <>)                of std_logic_vector(31 downto 0);     type bmatrix array (natural range <>, natural range <>)                 of std_logic;                       end package mat_pak;  library ieee; use ieee.std_logic_1164.all; use work.mat_pak.all;  entity newproj     generic ( size:  natural := 2 );     port (          clk:                in  std_logic;         clr:                in  std_logic;         start:              in  std_logic;         a_in:               in  matrix (0 size - 1, 0 size - 1);         b_in:               in  matrix (0 size - 1, 0 size - 1);         aplusb:             out matrix (0 size - 1, 0 size - 1);         parallel_add_done:  out std_logic     ); end entity newproj;  architecture behavioral of newproj     component add         port (             a:      in  std_logic_vector(31 downto 0);             b:      in  std_logic_vector(31 downto 0);             clk:    in  std_logic;             sclr:   in  std_logic;             ce:     in  std_logic;             result: out std_logic_vector(31 downto 0);             rdy:    out std_logic         );     end component;      signal temp_out: matrix (0 size - 1, 0 size - 1)                  :=  (others => (others => (others => '0')));     signal add_over: bmatrix (0 size - 1, 0 size - 1)                 := (others => (others => '0')); begin g0:      k in  0 size - 1 generate  g0x:          m in 0 size - 1 generate             add_instx: add                  port map (                     => a_in(k,m),                     b => b_in(k,m),                     clk => clk,                     sclr => clr,                     ce => start,                     result => temp_out(k,m),                     rdy => add_over(k,m)                 );         end generate;        end generate;      aplusb <= temp_out;  p1_add:     process (add_over)         variable check_all_done: std_logic;     begin         check_all_done := '1';         k in 0 size - 1 loop             m in 0 size -1 loop                 check_all_done := check_all_done , add_over(k,m);             end loop;         end loop;         parallel_add_done <= check_all_done;     end process;  end architecture behavioral; 

we find want , various rdy outputs (add_over array) together. in vhdl -2008 can done unary and, otherwise you're counting on synthesis tool flatten , (and do).

i made assignment aplusb concurrent assignment.

so dummied add entity empty architecture, above analyzes, elaborates , simulates, shows none of connectivity has length mismatches anywhere.